1. Field of the Invention
The present invention relates to a circuit for producing a video signal processing pulse, and more particularly to an improvement of a circuit for producing a gate pulse suitable for, for example, a pedestal level clamp operation in a television receiver.
2. Description of the Prior Art
In a television receiver, the pedestal level of a video signal is clamped at a given potential produced by a DC restoration circuit. The clamp operation is carried out in a pedestal level period of the video signal.
FIG. 1 shows an example of the conventional circuit for a pedestal level clamp operation. The circuit is comprised of a pedestal level clamp circuit 10 and a video signal processing pulse producing circuit 11. A composite video signal CVS with a pedestal level which should be clamped is applied to the pedestal level clamp circuit 10 through an input terminal 12 of the pedestal level clamp circuit 10.
The pedestal level clamp circuit 10 includes a brightness adjusting circuit, as described later. In the pedestal level clamp circuit 10, the pedestal level of the composite video signal CVS is clamped to a given potential under control of the video signal processing pulse producing circuit 11. The video signal processing pulse producing circuit 11 generates a gate pulse GP in response to a horizontal synchronous signal HSS applied to an input terminal 13 of the video signal processing pulse producing circuit 11.
The horizontal synchronous signal HSS is extracted from the composite video signal CVS in a conventional manner known to those skilled in the art. The gate pulse GP is applied to a control terminal 14 of the pedestal level clamp circuit 10. Then, the composite video signal CVS, which has its pedestal level clamped to the given level, is obtained from an output terminal 15 of the pedestal level clamp circuit 10.
Referring now to FIG. 2, the pedestal level clamp circuit 10 will be described below. In FIG. 2, an input terminal 12 of the pedestal level clamp circuit 10 is connected to the base of a transistor 16. The collector of the transistor 16 is connected to a power supply terminal 17. The emitter of the transistor 16 is connected to a ground potential terminal 18 through a level shift circuit 19.
The level shift circuit 19 is comprised of a series circuit of a resistor 20 and a transistor 21. The collector of the transistor 21, i.e., a connection node of the resistor 20 and the transistor 21, is connected to the output terminal 15 of the pedestal level clamp circuit 10, and also connected to a first voltage comparator circuit 22.
In the first voltage comparator circuit 22, a pair of transistors 23 and 24 are differentially connected to each other. The base of the transistor 23 is connected to the collector of the transistor 21. The base of the transistor 24 is coupled to a brightness adjustment circuit 25.
The brightness adjustment circuit 25 is comprised of fixed resistors 26 and 27 and a variable resistor 28. A movable terminal of the variable resistor 28 is coupled to the base of the transistor 24 for applying a brightness adjustment voltage V25. The variable resistor 28 is connected at its opposite ends to the power supply terminal 17 and the ground potential terminal 18 through the resistors 26 and 27, respectively.
A common connection node of the emitters of the transistors 23 and 24 is coupled to the power supply terminal 17 through a controllable switch 29 and a first constant current source 30, in series. The controllable switch 29 is connected to the control terminal 14 of the pedestal level clamp circuit 10. The collectors of the transistors 23 and 24 are connected to the ground potential terminal 18 through an active load 31, which is formed in a current mirror configuration by transistors 32 and 33. The transistor 32 is connected to the transistor 23 of the first voltage comparator circuit 22. The transistor 33 is connected to the transistor 24 of the first voltage comparator circuit 22 and to itself in a diode fashion.
The collector of the transistor 32, i.e., the connection node of the collectors of the transistors 23 and 32 is connected to a second voltage comparator circuit 34. In the second voltage comparator circuit 34, a pair of transistors 35 and 36 are differentially connected to each other. The base of the transistor 35 is connected to the collector of the transistor 32. Further, the base of the transistor 35 is connected to the ground potential terminal 18 through a capacitor 37. The base of the transistor 36 is coupled to a first reference voltage source 38.
A common connection node of the emitters of the transistors 35 and 36 is coupled to the power supply terminal 17 through a second constant current source 39. The collector of the transistor 35 is connected to the ground potential terminal 18 through a transistor 40. The transistor 40 is itself connected in a diode fashion and forms a current mirror circuit 41 together with the transistor 21 in the level shift circuit 19. The collector of the transistor 36 is directly connected to the ground potential terminal 18.
The operation of the pedestal level clamp circuit 10 will be briefly described below. A composite video signal CVS is applied to the base of the transistor 16 through the input terminal 12. The DC level of the composite video signal CVS is shifted by the level shift circuit 19. An output of the level shift circuit 19, i.e., a level shift video signal CVS' is introduced to the output terminal 15 and also applied to the first voltage comparator circuit 22.
When the controllable switch 29 is closed, the composite video signal CVS' is compared with the brightness adjustment voltage V25 of the brightness adjustment circuit 25 in the first voltage comparator circuit 22.
If the composite video signal CVS' is higher than the brightness adjustment voltage V25, a collector current I23 of the transistor 23 decreases to a level below the collector current I24 of the transistor 24. As a result, the collector voltage Vc32 of the transistor 32 is reduced. This causes the capacitor 37 to discharge its charge through the transistor 32 of the active load 31. Accordingly, the base voltage Vb35 of the transistor 35 in the second voltage comparator circuit 34 is reduced.
The base voltage Vb35 is compared with the reference voltage V38 of the first reference voltage source 38, which is applied to the base of the transistor 36, so that the collector current I35 of the transistor 35 increases. The collector current I35 is applied to the base of the transistor 21 through the current mirror circuit 41 and increases the collector current I21 of the transistor 21.
Due to the increase of the collector current I21, the voltage drop V20 in the resistor 20 increases. As a result, the level shift circuit 19 causes the level of the composite video signal CVS' to drop. Thus, the level shift circuit 19, the first voltage comparator circuit 22, the active load 31, the capacitor 37, the second voltage comparator circuit 34 and the current mirror circuit 41 comprise a negative feedback loop for automatically adjusting the output potential V15 of the output terminal 15 to the brightness adjustment voltage V25 of the brightness adjustment circuit 25.
According to the above operation of the pedestal level clamp circuit 10, the composite video signal CVS is automatically adjusted to the brightness adjustment voltage V25 so that the pedestal level of the composite video signal CVS is clamped at the brightness adjustment voltage V25.
Referring now to FIG. 3, the video signal processing pulse producing circuit 11 will be described below. In FIG. 3, the input terminal 13 of the video signal processing pulse producing circuit 11 is connected to the base of a transistor 42. The collector of the transistor 42 is connected to a power supply terminal 17. The emitter of the transistor 42 is connected to a ground potential terminal 18 through a parallel circuit of a capacitor 43 and a third constant current source 44. The base of the transistor 42 is further connected to a third voltage comparator circuit 45.
In the third voltage comparator circuit 45, a pair of transistors 46 and 47 are differentially connected to each other. The base of the transistor 46 is connected to the emitter of the transistor 42. The base of the transistor 47 is coupled to a second reference voltage source 48. A common connection node of the emitters of the transistors 46 and 47 is coupled to the power supply terminal 17 through a fourth constant current source 49. The collector of the transistor 46 is directly connected to the ground potential terminal 18. The collector of the transistor 47 is connected to an output terminal 50 of the video signal processing pulse producing circuit 11.
The output terminal 50 is connected to the control terminal 14 of the pedestal level clamp circuit 10 (see FIG. 1). The collector of the transistor 47 is further connected to the ground potential terminal 18 through a resistor 51. A transistor 52 is connected between the output terminal 50 and the ground potential terminal 18 in parallel to the resistor 51. The base of the transistor 52 is connected to the input terminal 13 of the video signal processing pulse producing circuit 11 through a resistor 53.
The operation of the video signal processing pulse producing circuit 11 will be briefly described below, in reference to FIG. 4. FIG. 4 shows waveform graphs of signals or voltages in the video signal processing pulse producing circuit 11.
When a horizontal synchronous signal HSS, as shown by a graph A, is applied to the base of the transistor 42 through the input terminal 13 at a time t1, the transistor 42 turns on. The waveform of an emitter voltage Ve42 is shown by a graph B.
Here, it is assumed that the emitter voltage Ve42 of the transistor 42 is V1 when the horizontal synchronous signal HSS has an amplitude of V1+Vf. The emitter voltage Ve42 is charged in the capacitor 43 so that the charge of the capacitor 43 is held at the emitter voltage Ve42 during the conduction of the transistor 42. The emitter voltage Ve42 is applied to the third voltage comparator circuit 45 and compared therein with a reference voltage V48 of the second reference voltage source 48.
When the emitter voltage Ve42 is higher than the reference voltage V48 of the second reference voltage source 48, the transistors 46 and 47 of the third voltage comparator circuit 45 are held in a non-conducting state and a conducting state, respectively.
When the horizontal synchronous signal HSS ends at a time t2, the transistor 42 is turned off. Then, the charge of the capacitor 43 is discharged through the third constant current source 44. The discharge proceeds gradually with a prescribed RC time constant of the parallel circuit of the capacitor 43 and the third constant current source 44. Therefore, the emitter voltage Ve42 gradually decreases, as shown by the graph B.
When the emitter voltage Ve42 is lower than the reference voltage V48 of the second reference voltage source 48 at a time t3, the transistor 47 is turned off.
The horizontal synchronous signal HSS is applied to the base of the transistor 52. Accordingly, the transistor 52 maintains an output potential V50 of the output terminal 50 to a ground potential V18 within the period of the horizontal synchronous signal HSS, i.e., the period between times t1 and t2.
After the time t2, the output potential V50 of the output terminal 50 rises to a prescribed voltage. The output potential V50 then lowers to the ground potential V18 when the transistor 47 is turned off at the time t3. As a result, the output potential V50 of the output terminal 50 has a waveform, as shown by a graph C. The output potential V50 is applied to the pedestal level clamp circuit 10 as the gate pulse GP for controlling the switching of the controllable switch 29. The gate pulse GP is produced a prescribed period after the horizontal synchronous signal HSS, as shown in FIG. 4. Thus, the gate pulse GP is obtained during a period corresponding to the pedestal level of the composite video signal CVS.
As is described above, the gate pulse GP for controlling the pedestal level clamp circuit 10 is produced by using the horizontal synchronous signal HSS. Therefore, the pedestal level clamp circuit 10 fails to carry out the automatic pedestal clamp operation when the horizontal synchronous signal HSS is not obtained.
The no-signal condition of the gate pulse GP occurs, for example, when a television receiver is changed to a video mode for displaying video images reproduced by a video tape recorder but the input terminals of the television receiver are left open without being coupled to the video tape recorder.
Referring now to FIG. 2, when there is no input of the GP to the control terminal 14, the controllable switch 29 is held in an open state. Then, the current mirror circuit 41 is charged by the base current Ib35 of the transistor 35. The base voltage Vb35 of the transistor 35 increases according to the charge of the capacitor 37 until the base current Ib35 becomes zero.
The transistor 35 is turned off when the base voltage Vb35 becomes higher than the reference voltage V38 of the first reference voltage source 38. At this time, the collector current I35 of the transistor 35 becomes zero so that the collector current I21 of the transistor 21 also becomes zero. This causes the collector voltage Vc21 of the transistor 21 to increase to a potential the same as the emitter voltage Ve16 of the transistor 16.
The collector voltage Vc21 of the transistor 21 with the emitter voltage Ve16 is applied to the first voltage comparator circuit 22, but the collector voltage Vc21 is not adjusted to the brightness adjustment voltage V25 by the feedback circuit. This is because the first voltage comparator circuit 22 is held in the non-operating state due to the open state of the controllable switch 29. Therefore, the pedestal level clamp circuit 10 changes the image display screen of the television receiver to an excessive bright condition, irrespective of the adjustment of the brightness adjustment circuit 25.
The practical effect of this condition is that the frequent change of brightness of the display screen may cause more rapid failure of the screen or other television receiver components. In addition, the power consumption of the television receiver is increases.